Preliminary results from Professor Magnus Själander at the Computer Architecture Lab at NTNU indicate that QERV is more than three times faster, and twice as power efficient per instruction at an additional area cost of only 13% compared to SERV. This means that it’s still the world’s smallest RISC-V CPU, only faster.
A 4-bit version has been a most requested SERV feature for a long time. SERV architect and lead designer Olof Kindgren says: “Earlier this year I asked a Qamcom colleague to look into this. Just a few days later he presented me with a mostly working implementation and we were happily surprised to see that the results looked better than we had expected. This gave us the confidence that we were on the right track and started work to finish the implementation.”
QERV is still in a testing phase and expects to see further size reduction and performance improvements in the coming months, but is ready for integration testing and already sees interest from the users. “As a leading edge design house, we always make sure to have the best tools for every task, and QERV fills a gap when it comes to PPA trade-offs. This work is also in line with our commitment to be RISC-V experts” says Qamcom CEO Johan Lassing.
Due to its low complexity, SERV is a popular choice for novel process technologies and QERV intends to fill this role as well. “The low gate-count of SERV is a great match for anyone developing a RISC-V-based processor in our low-cost FlexIC technology. QERV, the 4-bit version of SERV, will boost the performance considerably for many wearable computing applications whilst minimising the area overhead.” says Emre Ozer, Senior Director, Processor Development at Pragmatic Semiconductor.